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Pcbnew

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Contents

[edit] Related kicad pages

[edit] Layers

Probably the best place to start is to look at the layers used in PcbNew. Under preferences/colors you will get a list of all the 28 layers and the associated colors.

Some of the Nomenclature needs clarification:

  • Copper Layers - This is what other packages might call Tracks - does not include pads and via pads - limit to become 64,000+
    • Front
    • Back
    • Inner_Lx Are inner connecting copper layers where 'x' refers to which layer.
  • Tech Layers
    • Adhes_Cop is the Adhesive screen on the 'solder side'. Normally there would be no adhesive on this side unless the part is flipped to the opposite side.
    • Adhes_Cmp is the Adhesive screen on the normal part side.
    • SoldP_Cop and SoldP_Cmp - Solder paste masks
    • SilkS_COP and SilkS_Cmp - Silk Screen
    • Mask_Cop and Mask_Cmp - Solder Mask screens (Negative Image )
    • Drawings - Dimensions etc
    • Plating (coming soon)
    • HoleFill (coming soon)
    • KeepOut for component, plane, trace and via keepouts and keepins. (coming soon)
    • ViaPlug (coming soon)
    • Contacts (coming soon)
    • PeelMask (coming soon)
    • Finsh (coming soon)
    • Courtyard for component courtyards (coming soon)
    • Component for component outlines for assembly drawings (coming soon)
    • Coating (coming soon)
    • Probe (coming soon)
    • Fixture (coming soon)

[edit] Displaying layers

Pcbnew can displays technical layers ( like solder mask ) bur only in "hight contrast mode"

  • Select "hight contrast display mode"
  • Select the technical layer you want to see.

Pads ( and all items) that are on the selected layer are shown using this layer color Others are displayed in dark gray color.

Of course, in normal display mode, these layers are not displayed.

[edit] Board design Steps

[edit] Setting up DRC(Design Rules Check)

[edit] Importing Netlist and associated dialogs

  • Make sure the librarys and paths are set correctly
  • Basic Reading of the netlist
click on the netlist button and look at the dialog
select netlist file
  • Net changes
Bad Tracks Deletion needs to be set to "Delete"
Exchange Module 
Change allows updating modules
Extra Footprints 
Keep allows keeping of hardware holes etc..
Timestamp 
This causes the modules to be identified by their timestamp rather than the reference number. uesed when there are changes to the Reference numbers - back up first before trying this.
Rebuild Board Connectivity
Reconnects the board parts based on _______ ?(net list? any exceptions? ) - need a precise explanation of what happens here.
Footprint test
Returns no modules if non found. What else?

[edit] Placement

[edit] Routing

[edit] Hand Routing

  • Magnetic tracks ??
  • edit/Cleanup_tracks_and_via
    • Be aware that those extra via's used to put in test points or stitch ground planes can be deleted here.
    • The connect to pads option is very useful if you have changed to smaller resistor or capacitor cases.

[edit] Auto Routing

[edit] Freerouter

Most people are using Freerouter.

  • Paths and zones placed before routing are left alone.
[edit] Built-in Auto Router

[edit] Creating Copper Ground planes - Zones

  • Select Add Zones icon
  • Trace the limit of the zone
  • Place the cursor on a pad belonging to the net you want for the plane, (GND or any other)
  • Click right on the zone and select fill zone
  • Also see Connecting different net planes with a Pavilion AKA Net-Tie

[edit] Vias

[edit] Alternate Via Drill

From the Tracks and Vias Sizes dialog box:

This feature is used when some vias must have a specific drill size (which differs from the default drill size). You can adjust the "Alternate Via Drill" to a correct value, and for some vias you can select this alternate value (by the pop-up menu) This job is more easy if you have chosen a bigger (or smaller) via diameter for theses vias, because the pop-up menu has a command to export the current via drill to all vias which have the same diameter (put the mouse cursor on such a via, and by the pop-up menu (edit via option) select the alternate via drill for this via, and export the via drill to other identical vias (command edit via/export via drill to other id vias)

[edit] Working with 4 layer boards

[edit] Setting up power layers
[edit] Setting up mixed layers

[edit] Panelize PCB

There are times when you want to put several copies on one pannel.

  • Open PCBnew and display your board.
  • Use select tool (arrow icon top of right hand icon bar) left click and draw a box around your board release mouse button
  • move highlighted block OFF the drawing page somewhere this just gets it out of the way. You will get a move block requestor, make sure all

options are ticked and click OK. Your board layout will then move.

  • File menu > Append Board, then select the .brd file of your PCB then open.

A copy of your PCB will appear in the centre of the drawing page (that's why we moved the first copy)

  • Use the block move method again to position your board where you want it,

then move the first copy back onto the board.


  • Of course you can repeat this as many times as you want.

This method works if you want to place several different boards onto one drawing.

Another method if you want a copy of the same board, is to block select your board in the same way, then move it to the position you want, but instead of left click, right click and you will get a context menu. select copy block, and your board will be copied to the new location.

[edit] CAM Plot, Drill

  • Do checks
  • Set Pads Mask Clearance
What exactly does "Solder mask ratio clearance mean?
Hole count
The number of holes in the PCB is found in the -drl.rpt file. They are listed by number and size.

[edit] Fiducial Marks

No one has ever asks for fiducials - and they spend time removing them and putting in their own. But if you insist: Global and/or panel fiducials should ideally be located at three points of the grid. Locate a lower left fiducial at the 0,0 datum point and two fiducials located in positive X and Y directions. These three marks help for correcting of non-linear distortions (scaling, stretch and twist).

Global fiducials should be located on all PCB layers that contain components to be mounted with automated equipment. Using other circuit objects (via-holes, etc.) ends up being a compromise.

[edit] Module Position File

[edit] Modedit

This is to create the modules AKA footprints.

  • A Pad with pin number 0 is not connected to any net - for structural use.

[edit] Module fields Reference and Value

  • The field that has the module name becomes the reference designator (R1 for a resistor). The field that contains: 
  VAL**

reflects the Part name that pointed to the module.

[edit] Insert attibutes

Under module_editor/module_properties/attributes

  • Normal is the standard attribute.
  • Normal+Insert indicates that the module must appear in the automatic insertion file (for automatic

insertion machines) This attribute is most useful for surface mount components (SMDs).

  • Virtual indicates that a component is directly formed by the circuit board. Examples would be edge

connectors or inductors created by a particular track shape (as sometimes seen in microwave modules).

  • What is the difference between Normal and virtual - Virtual is for an edge card connector - but what is different?

[edit] Hole Types

  1. Standard - through hole pad
  2. SMD Surface mount (no hole) Hole has an electrical connection (used for through hole devices and/or Ground points)
  3. Connector - perhaps for an edge card connector??

[edit] Library Generation Considerations

Do not trust what is in the supplied library.

[edit] Creating IPC compliant modules

To create foot prints that comply with ipc specs get LP Calculator or Lp_calculator_V2009 http://www.oldversion.com/PCB-Matrix-LP-Calculator.html(these run under wine on linux).. There are three versions of the modules one can create for surface-mount work - General purpose - high reliability and very-high density. (There are settings to get these numbers out of LP-calculator).

  • A = Most - reliable - but bigger
  • B = Nominal - mid sized
  • C = Least - very small

One important detail: these case sizes originate in metric - the imperial notation is approximate. There are two ways that cap footprints are specified - and it can generate confusion - metric and imperial - thus 0201 (02x01mils) = 0603 in metric (remind me to once again curse the creeps that stopped metrication back in the '60s). Kicad's naming should be based on the modern metric codes. Thus a 0603 becomes 1608M and there should be three versions of the decal:

1608MM - most sized
1608MN - Nominal sized
1608ML - least sized

Going on step further we could have

1608MN02 be a metric 1608 Nominal sized land with 0.2mm thick so it can match something in the 3D renderer.

I could also see having three libraries - as the SNM7351A SNL7351B SMN7351C.

Complete list of SMT_Case_Size_Codes

pcb-fpw is sort of an opensource version of LP_calculator. Download link pcb-fpw.

All of it is for supporting IPC-7351. pcb-fpw was written to support the competing opensource 'pcb' package - might work to have a script to translate the modules?

pcb-fpw is open source, so it would be possible to modify add it to the kicad suite .. seems to be written in java-bloat.

The separate names for a cap and resistor 0805 package seems silly unless we are using polarized caps. In which case we could have

P1608MN02

And a diode in such a case

D1608MN02

The M,N,and L are for most, Nominal and least -- describes most compromises folks would run into..

The modules should have a minimal silk screen and a part outline on the drawing level.

Custom case numbers that should probably be organized via part vendor.

[edit] Tricks

[edit] Preventing Thermals on heatsinking pads of SM packages

MLF/QFN devices, which have a thermal pad on the middle of the bottom. There are two considerations here.

  1. There is the heatsinking requirement
  2. A poor copper design wrong the chip will float on a central blob of solder, resulting in unreliable soldering of the pins.

For the thermal pad footprint for a 32 pin device arrange 8 square pads around a central via, and place solder resist over the via Tented Via with the outer edge of all the pads matching the pad on the bottom of the chip. The breaks in the pad to pad area limit the height of the solder ball due to surface tension so the chip sits lower and closer to the board.

Number all the (thermal) pads as "33", so there is only one extra pin in eeschema. Connect together the pads and the via with a grid of thick tracks. The use of a tented via in this way means that the via will be solidly connected to the heat-sinking copper zone on the reverse side, whilst the tenting prevents solder wicking through the via. One could also put a via for all 9 locations bringing more heat to the opposite side of the PCB.

mlf


similar advice here

[edit] Via in pad

[edit] Importing DXF - DWG

[edit] Current rating rule of thumb - trace width - via size

  • 100mils of 2oz copper will approximately carry 10A with some 20deg C temperature rise.
  • Finished diameter of the via hole should be at least as large as the trace-width/3!

[edit] Checklist

[edit] Part Placement

  • SMD component orientation consistent
  • Clearance for IC extraction tools, heatsinks etc.
  • Polarization of components checked
  • Are components on grid ?
  • Check the orientation of all connectors - is Pin #1 where you expect it?
  • <inimum component body spacing
  • Bypass capacitors located close to IC power pins
  • Series terminators are located near the source
  • I/O drivers near where their signals leave the board
  • PCB has ground turrets, power rail test points, and test points for important signals, all labeled
  • EMI and RFI filtering as close as possible to exit and entry points in shielded areas
  • Potentiometers should increase controlled quantity clockwise
  • Mounting holes electrically isolated or not?
  • Mounting hole clearance for hardware
  • SMD pad shapes checked
  • Tooling holes for automated assembly
  • Extra clearance for socketed ICs
  • Pin one pad indicators

[edit]  Routing

  • Digital and analog signal commons joined at only one point - net tie - ground Pavilion
  • Check for traces running under noisy or sensitive components
  • No vias under metal-film resistors and similar poorly insulated parts
  • Traces spaced to max where possible
  • Check for dead-end traces, unless used on purpose
  • Ensure schematic software did / did not separate Vcc from Vdd, Vss from GND as needed (Not a problem if you don't use invisible connections - it really doesn't save time in the long run )
  • Multiple vias for high current and/or low impedance traces - check the current ratings of your via size

[edit] Current rating of Traces, viass

[edit]  Dimensions

  • Hole diameter on drawing are finished sizes, after plating.
  • Finished hole sizes are >= 0.25mm larger than lead
  • Silkscreen legend text weight, spacing
  • Pads >=0.37mm larger than finished hole sizes
  • Components spacing from edge of PCB
  • Traces to board edge spacing
  • Consider Drill size tolerance
  • Soldermask clearance and tolerance - often board houses want zero clearance.
  • High voltage traces need extra spacing

[edit] Text on Silk Screen and other Layers

  • Allign legend text tp read from one or two orientations
  • Logo in silkscreen legend
  • Copyright notice
  • PCB part number and version
  • Do parts cover Legend
  • Label all layers - Mirror text on back
  • Pin one indicators
  • High pin count parts can have corner pins numbered for ease of location
  • Silk screen tick marks for every 5th or 10th pin on high pin count Parts

[edit]  Other

  • CAD design rule checking must be turned on
  • High frequency circuitry precautions observed
  • ReadMe for PCB house see Gerbview#What_to_send_the_PCB_house checklist
  • Thermal reliefs for internal power layers
  • Solder paste mask spacing
  • Blind and buried vias on multilayer PCB
  • PCB layout panelization
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